基于FPGA的半硬回收数据采集存储系统设计

Design of half-reclaimable data acquisition and storage system based on FPGA

  • 摘要: 文章介绍了基于FPGA的半硬回收数据采集存储系统的多片A/D数据编码技术、有限硬件资源下的大容量Flash读写技术、USB接口设计。利用VHDL语言和QuartusⅡ7.1软件完成了系统设计及软件仿真。实验表明:所设计的系统实现了16通道10 kHz的数据采样和存储,与计算机接口数据传输速率达8 Mbit/s,系统运行稳定可靠。

     

    Abstract: This paper discusses multi-A/D data coding, reading from and writing into large capacity flash memory in finite hardware resource, USB interface design of half-reclaimable data acquisition and storage system based on FPGA. The system was modularly designed with VHDL and QuartusⅡ7.1 software. The test results show that the system can perform data acquisition and storage of 16 channels with 16 kHz sampling frequency, with speed of 8 Mbit/s with communication to computer, and with a proven system reliability.

     

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