Abstract: The influence of the distance between the sensitive nodes, the hardening structure, and the test data mode on the single-event-upset (SEU) sensitivity of the D flip-flop chain fabricated with 65 nm bulk silicon CMOS technology are studied by using the pulsed laser. The experimental results show that the increase of the distance between the sensitive nodes can effectively improve the resistance against the SEU of the DFF with dual interlocked storage cell(DICE) structure, but the good effect will be reduced when the spacing is larger than 4 μm. Besides, the SEU sensitivity of the DFF hardened by the guard ring (for the PMOS transistor) or by the guard drain (for the NMOS transistor) is found to be significantly reduced. It is also found that the SEU sensitivity of the DFF chain varies with the test data mode, suggesting a dependence of the type of the sensitive transistor in the DFF under different test modes. In addition, the pulsed laser, as a ground simulation method, can be used to effectively determine the optimal spacing in the design of the SEU sensitive devices and to verify the related protective effects.